In manufacturing memory devices, several stages are employed. At an early stage in the process, called probe, it is typical to test a memory array for defects. If an address is identified as defective, the row or column associated with the defective address is typically disabled in favor of a redundant row or column, as applicable. This is accomplished by programming the address associated with the defective row or column into the memory, such as to assign the address associated with the defective row or column to the redundant row or column. Such programming may be accomplished by programming a bank of fuse and/or antifuse elements or programmable elements such as nonvolatile memory. In this manner, once a defective address is received to a memory, the defective address is remapped to a redundant element address associated with the fuse and/or antifuse bank. This process of remapping defective memory array elements to redundant memory array elements is well known in the manufacture of memory devices, especially dynamic random access memory (DRAM) devices.
Later in the manufacturing process, a memory array is typically tested again. Often such a test reveals defects previously not discovered at probe. Again, if a defect is found in the memory array requiring remapping to a redundant element, a bank of programmable elements is programmed with the defective address. However, if the defect discovered at the latter test step is in actuality a defect in a redundant element (i.e., a redundant memory element in an array designated to replace or repair a defective prime memory element in the array), then an error would exist with respect to two separate redundant banks enabling separate redundant elements for a single address.
To avoid this error, test circuitry has been introduced within some memory integrated circuits. Such test circuitry provides information as to whether a redundant element is already enabled. By testing a particular address, the test circuitry indicates whether the address is associated with a redundant element. As the address to the defective memory element is programmed into a bank, the test circuitry makes it possible to identify which bank is programmed with the address. To identify which bank is programmed with the defective address, all banks are typically logically OR'd together. A test may be employed to ensure that no two banks are activated for the same defective address. For example, if a defect is found in a memory array and a redundant element is to be enabled therefor, a test is employed to determine if such address has already been programmed to a bank. If so, it means that the redundant element associated with the bank is defective too. Consequently, the bank is disabled in favor of a new bank associated with a new redundant element. Such a repair to a repair may be effected in part by programming an antifuse to disable the previously enabled bank.
However, to avoid the above-mentioned error of enabling two redundant elements for the same address, these circuits have required a significant amount of test mode circuitry in the memory device, and have further required significant lengthening of test mode time for the device. Consequently, it would be desirable to avoid introduction of such test mode circuitry and to reduce test mode time, and still be able to avoid the error of having two or more redundant elements enabled for a single defective address.